Technology advisor and Automation expert. 20+ years of experience in innovative cross-domain solutions
delivery, cost reduction and automation. In depth expertise in EDA tools, semi-conductor design
methodologies, web technologies, UNIX variants and network computing with general expertise in several
different technology domains.
Technology visionary at heart, I am always working on or advising on new ideas, supported by my core
expertise, ability to quickly develop rapid prototype and foresee the usability aspects.
My Work:
Outlined and presented innovative ideas to top management. Managed, trained and mentored large group of
engineers. Created and delivered tailored solutions and training.
Played a variety of roles from:
- idea to implementation in semiconductors
- solution architect to hands on developer in EDA and web technologies
- hands on hardware assembly to design and management of server room
- mobile technology and solutions advisor to hands on developer
- general technology advisor in a variety of fields
Implemented methodologies for:
- Analog, Digital and Mixed Signal Designs
- Packaging and Board Design
- Extraction & EM/IR Analysis
- Simulation
- Verification
- Chip Integration
Domain Expertise:
- EDA Vendors, solutions, tools and flows
- Design Cycle Improvement
- Design Reuse
- Semi-Conductors
- Fab and Packaging
- Web Design
- Hardware, OS and Networks
- Information Technologies
- Information networks
- Network Architecture
- Usability Studies and Improvement
- QA Engineering and Management
- Machine learning with Octave and Matlab
Specialties: Cost reduction through automation, technology visionary and innovator with focus in mobile,
cloud computing, internet, EDA and semiconductors. Statistical data analyses, data normalization, automation
and machine learning.
13 yrs 8 mos
Full-time
Apr 2021 - Present
Austin, Texas, United States
Solutions & Automation
=> Learn from SMEs,
=> Analyze work flows,
=> Identify automation candidates,
=> Identify efficiency boosters,
=> Rapid Prototypes
=> Solution Validation
=> Scale utilizing Multi-Data-Center Global Infrastructure
=> Centralized On-Demand Report Generation
=> Incorporate Feedback
=> Repeat
"Automation is the work of skilled handyman who could translate knowledge and intelligence contributed by
Subject Matter Experts into a feedback driven, agile and scalable solution."
Solutions Architect - Design Automation, Optimization, Regression, RCA, Engineering Management, IT
Infrastructure, Cloud Computing, HPC, CI/CD, LAMP, Data Analytics, Reports,Solutions & Automation => Learn
from SMEs, => Analyze work flows, => Identify automation candidates, => Identify efficiency boosters, =>
Rapid Prototypes => Solution Validation => Scale utilizing Multi-Data-Center Global Infrastructure =>
Centralized On-Demand Report Generation => Incorporate Feedback => Repeat "Automation is the work of skilled
handyman who could translate knowledge and intelligence contributed by Subject Matter Experts into a
feedback driven, agile and scalable solution." Solutions Architect - Design Automation, Optimization,
Regression, RCA, Engineering Management, IT Infrastructure, Cloud Computing, HPC, CI/CD, LAMP, Data
Analytics, Reports,
Oct 2014 - Present
San Francisco Bay Area
IP design is constantly pushing limits to reach out higher speeds, more bandwidth, less power while spreading
implementation to advanced nodes, This requires forward looking, always improving, design and execution
strategy. In this complex minefield of challenges, collaboration and cost, I work horizontally and in
multiple verticals.
Primary Responsibilities:
- Design IP release management.
- Design IP distributed dependency management
- Design IP Trend Analyses - QoR improvement
- Design IP Execution Analyses
- Design IP Quality and on-time Delivery
- IP Design Methodology improvement
- IP Quality and Standardization.
- IP Design Data Centralization and Distribution
- Synergy between EDA tools and IP Design
- Return-on-Investment Improvements
- Cloud Infrastructure, ACL, Networks, Linux
- Third Party business, IP and licensing
- Big Data and Analytics.
Focus Areas: Design Automation, A/MS Library Characterization,Synthesis, STA, IP release and packaging, IP
Quality, Standardization, Productivity Improvement.
Collaborating with team members to ensure, Predictable, Trackable, Timely IP Release with-Quality, Execution
and Delivery of IP.
Nov 2010 - Present
San Jose
Working in Mixed Signal Services group, utilizing depth and breadth of expertise for timely delivery of chips
and methodologies for semi-conductor design houses and foundries.
Typical delivery includes, a mix of expertise in following:
Custom Design:
Specs -> Schematic -> Simulation -> Layout -> Verification -> Extraction -> Post Layout Sims -> EM/IR
Digital:
RTL -> Synthesis -> PnR
Verification, Logical Equivalence, Simulation, Test Documents
Silicon Testing:
Chip Bringup -> Parts Selection -> Automated test, measurement, calibration, statistical analysis
Scripting:
SKILL, SKILL++, perl, tcl, python, shell, etc
OS, Networks and Storage:
Unix/Linux variants, LAN/WAN, SAN / NAS
Platforms:
Virtuoso, Encounter, Incisive, third party.
Jan 2014 - Oct 2014
San Francisco Bay Area
Senior Principal Design Engineer
Business, Engineering, Methodologies and Fun.
Sep 2001 - Aug 2006
- Working in several different roles with focus on eliminating hurdles between idea and implementation.
Reducing design cycle and improving time to market.
- President's Club Award in year 2002. I believe, it's is the highest level of recognition with in the
company.
- Intranet Hobby Project: Leo.Cadence.COM. Regularly used by over 90% of the company world wide.
Aug 2006 - Nov 2010
Working with semiconductor design houses, to help align product design cycle time with their business
requirement, by analyzing current strategy and translating schedule slipping hurdles into technical
challenges, which in turn are solved by introducing automation, expert assistance, filling the gaps in EDA
design tools, improving methodology, automating parallel simulation and automatic verification runs.
Harnessing the power of cloud computing for parallel processing, web technologies for reporting easy to
understand analytical data point comparison and developing scripts to make it all work together. RDBMS,
spreadsheets or unix directory structure is used for data management and establishing hand-off mechanism
between different stages.
Area of expertise:
- results based big picture approach, as opposed to task based.
- chip integration and ECO management.
- bump extraction, verification and packaging data generation.
- design migration from one process to other.
- utilize leading and emerging EDA solutions to overcome design challenge.
- general design flow improvement and database management.
- establishing a hand-off mechanism.
- automated mixed signal flows.
- automation, regression and QA.
- productivity enhancement tools and scripts.
- improving schematic and post layout simulation run time.
- parallel simulation and reporting for coverage and optimization.
- layout processing to gather statistical data.
- automated physical verification.
Aug 2006 - Jul 2010
Reported to VP of Engineering, facilitated implementation and testing of 10G‐BASE‐T phy. I was responsible
for enabling the company to be productive on advanced technology nodes, in a multi‐vendor flow. Worked on
90nm, 65nm, 40nm and 28nm process nodes with IBM, Chartered and TSMC foundries. CAE ( Computer Aided
Engineering ) management involved all aspects of making the chip successful. My management responsibilities
included successful implementation ,integration and testing of our chips. Played key role in tool, vendor,
resource and methodology selection. Worked with tools and IPs from Cadence, Mentor, Ansys, Mathworks, AWR,
CST, Magma, Synopsys. Extended automation to silicon bring-up, parts selection and calibration. Implemented
semi-automated chip production flow. Built and managed mini data center with high performance servers and
storage.
Highlights:
- automated chip production flow.
- technology node advancement from 130nm to 28nm.
- multi-vendor tools, technologies and flows
- automated parallel simulation flow for circuit optimization and corners analysis, using ocean and perl
- aided physical design with productivity enhancement tools & utilities
- designed MSoT, DoT and spice in the middle flows
- implemented extraction and post layout back annotation flow
- implemented post‐layout‐simulation flows for connection correctness and accuracy
- automated chip integration flow, overcoming tool capacity and performance issues.
- automated physical verification flow for bottom‐up and top‐down chip verification
- automated RTL synthesis flow for sweeping through a set of constraints to find most optimum solution
- automated placement strategies to overcome design congestion issues.
- automated inductor modeling and technology file generation for EM solvers
- identified, interviewed and helped in finding appropriate employees and consultants.
- managed IT services and infrastructure
- managed internal and external physical design groups.
Jan 1998 - Sep 2001
Consultancy positions in Semi-Conductors Industory for:
- Support : Semi-conductor design, technology, tool support.
- Education : Delivering IC design tools related courses.
- Methodology: Tool Design and Development.
- Design : Automation and Test Procedure development.
1998 - Sep 2001
BRI Inc. is now known as CMC Americas.
Consultancy positions in Semi-Conductors Industory for:
- Support : Semi-conductor design, technology, tool support.
- Education : Delivering IC design tools related courses.
- Methodology: Tool Design and Development.
- Design : Automation and Test Procedure development.
1996 - 1998
Worked on the following:
1. IBM Mainframes and Digital VAX/PDP systems maintenance.
2. WAN and LAN, design and maintenance.
3. Electro-Mechanical Systems, improvement and support.
4. PC assembly, Hardware and circuits troubleshooting.
5. Worked with systems for Navy, Weather, Hospitals etc.
6. Development, Maintenace and troubleshooting on windows, HPUX, AIX, Solaris, etc. using C language and
shell (sh,ksh,csh,awk,sed) programming.
1994 - 1996
School of Electronics
Jul 1990 - Jun 1994
2004 - 2004
Jul 1986 - Jun 1990